Integrated circuits have progressed to advanced technologies with smaller feature sizes, such as 32 nm, 28 nm and 20 nm. In these advanced technologies, the gate pitch (spacing) continuously shrinks and therefore induces contact to gate bridge concern. Furthermore, three dimensional transistors with fin-type active regions are often desired for enhanced device performance. Those three dimensional field effect transistors (FETs) formed on fin-type active regions are also referred to as FinFETs. FinFETs are required narrow fin width for short channel control, which leads to smaller top S/D regions than those of planar FETs. This will further degrade the contact to S/D landing margin.
Along with the scaling down of the device sizes, such as in deep micro technology, the contact size was continuously shrunk for high-density gate pitch requirement. To shrink the contact size without impacting contact resistance, the long contact shape was proposed for 32 nm and beyond technologies. Long contact shape allows tight width dimension on the gate pitch direction but increased length on the gate routing direction to extend both contact area for source/drain and exposure area in the lithography patterning process. Long contact shape can achieve both high gate density and lower contact resistance. However, there are concerns due to the space limitation of line-end side. In line end, the concerns include line-end shortening and line-end to line-end bridging, leading to either contact-to-fin active connection opening (shortening) or contact-to-contact leakage (bridging). To reduce the line end shortening improve, it requires a wider space rule or more aggressive reshaping by optical proximity correction (OPC) on the line end, which will impact the cell size or cause bridging in a given cell pitch. This is getting even worse on future fin-type transistors because fin-type active regions are very narrow.
Therefore, there is a need for a structure and method for fin-type transistors and contact structure to address these concerns for enhanced circuit performance and reliability.